Abstract
High-performance analog-to-digital converter integrated circuits are in high demand because of new uses in wireless communications, broad band transceivers, digital-intermediate frequency (IF) receivers, and many other digital devices (ICs). Resolution, sampling rate, and power consumption all need to be at their best for these ICs. The goal of this research is to find a way to design a pipeline analog-to-digital converter (ADC) that uses the least amount of power and still has a good speed and resolution. In this study, a 14-bit resolution pipelined analog-to-digital converter (ADC) is built.