Multi-channel UART with auto baud rate detection

Authors: Mayuri Patil, Ashish Ranjan

Certificate: View Certificate

Abstract

This project is about the design and implementation of a Multi-channel UART with automatic baud rate detection. To meet modern complex control systems communication demands, the project presents a multichannel UART controller based on FIFO (First In First Out) technique and FPGA technology (Field Programmable Gate Array). It is designed with FIFO circuit block and UART (Universal Asynchronous Receiver Transmitter) circuit block within FPGA to implement communication in modern complex control systems quickly and effectively. This controller can be used to implement communication when master equipment and slave equipment are set at different baud rate. It also can be used to reduce synchronization error between sub-systems in a system with several subsystems. The controller is reconfigurable and scalable. Now a days electronic systems are getting complicated wherever it’s used e.g. home, automobile, aerospace etc. Most of the peripherals is having UART interface e.g Camera, Bluetooth device, Wi-Fi device etc. Most of the time we have limited UART port on board mainly 2 or 3 that limits the capability of the system. Through this proposed system, we can configure N no of UART channel with flexible baud rate. Most of the peripheral requires a variable baud rate system as per speed requirement but mostly baud rate of UART can’t be changed at run time. Through this system, we have automatic baud rate detection and hence it is possible to switch between different baud rates.

Introduction

A UART (Universal Asynchronous Receiver/Transmitter) is the microchip with programming that controls a computer's interface to its attached serial devices. Specifically, it provides the computer with the RS-232C Data Terminal Equipment (DTE) interface so that it can "talk" to and exchange data with modems and other serial devices. As part of this interface, the UART also Converts the bytes it receives from the computer along parallel circuits into a single serial bit stream for outbound transmission On inbound transmission, converts the serial bit stream into the bytes that the computer handles adds a parity bit (if it's been selected) on outbound transmissions and checks the parity of incoming bytes (if selected) and discards the parity bit adds start and stop delineators on outbound and strips them from inbound transmissions. Handles interrupts from the keyboard and mouse (which are serial devices with special ports) .May handle other kinds of interrupt and device management that require coordinating the computer's speed of operation with device speed serial transmission is commonly used with modems and for non-networked UART is a device that has the capability to both receive and transmit serial data. UART exchanges text data in an American Standard Code for Information Interchange (ASCII) format in which each alphabetical character is encoded by 7 bits and transmitted as 8 data bits. For transmission the UART protocol wraps this 8 bit sub word with a start bit in the least significant bit (LSB) and a stop bit in the most significant bit (MSB) resulting in a 10 bit word format. a reset and attempts to obtain the satellite signals and calculates a new position.

Conclusion

From result of proposed work it is concluded that the design uses VHDL/Verilog language to acquire the modules of universal asynchronous receiver transmitter. By Using the Xilinx software to complete simulation. The results are stable and reliable according to binary information. The outcome is feasible and efficient with power reduction and also area reduction. Especially in the field off electronic design technology has recently become widely used, this design shows great significance and can be used in various applications.