TIQ Comparator Based Performance Analysis of Pipeline Analog to Digital Converter

Authors: Deeptansh Tripathi, Shivraj Singh

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Abstract

High-performance analog-to-digital converter integrated circuits are in high demand because of new uses in wireless communications, broad band transceivers, digital-intermediate frequency (IF) receivers, and many other digital devices (ICs). Resolution, sampling rate, and power consumption all need to be at their best for these ICs. The goal of this research is to find a way to design a pipeline analog-todigital converter (ADC) that uses the least amount of power and still has a good speed and resolution. In this study, a 14-bit resolution pipelined analog-to-digital converter (ADC) is built. The pipelined architecture makes it possible to get both high speed and high resolution. Pipeline ADC is used because it can make some parts of flash ADC easier to use. Calibration steps have a big effect on the absolute and relative accuracy of pipelined ADC. This paper shows an example of a 14-bit, 80-Megabit-per-second ADC made with CMOS technology and a 0.18-micrometer pitch. The converter has seven pipelined stages, and each stage uses 0.18 CMOS technology to implement two bits.

Introduction

Popular among ADCs requiring resolutions of 8 to 14 bits and sampling rates between a few MS/s and hundreds of MS/s is the pipelined topology. Its popularity can be ascribed to its relatively simple and repeating interior architecture, as well as a notable reduction in the number of comparators necessary to attain a fixed resolution when compared to other Nyquist-rate data converters such as Flash, folding interpolating, etc. Mobile systems, CCD imaging, ultrasonic medical imaging, digital receivers, pedestal stations, digital video (e.g. HDTV), xDSL, cable modems, and fast Ethernet are examples of applications that utilise pipelined ADCs [1]. With the use of pipelined ADCs in several consumer items, research into enhancing the performance of pipelined ADCs has received a great deal of attention over the past decade, with linearity improvement and power reduction being the most commonly explored areas. With deeper submicron technology, low inherent gain, low supply voltages, and device mismatch have made it difficult to achieve extremely linear data converters (i.e., >10-bit linear) using typical pipelined ADC design. Low power consumption in pipelined ADCs is inspired by the prevalence of pipelined ADCs in mobile systems, where low power consumption permits longer battery life and consequently greater consumer efficiency. In agitated systems in which a large number of ADCs may be integrated on-chip simultaneously, enormous net supremacy expenditure might generate large amounts of heat, necessitating expensive packaging for heat dissipation. Thus, approaches that lower the power consumption of pipelined ADCs make mobile and wired integrated circuits more cost-effective. The pipelined ADC topology is utilised to derive and demonstrate an alternative approach to standard quantizes based on accurate analogue signal processing. By outsourcing various precise requirements from the analogue domain to the digital domain, the suggested converter may take advantage of the scalability of technology rather than being hampered by its constraints. In recent years, more and more system functionalities have been incorporated onto a single chip, as electronic systems have become increasingly complex and very deep submicron technology have made this possible. Therefore, mixed signal Integrated Circuits (ICs) that integrate digital and analogue components on the same substrate are widely used. Other than the extreme density

Conclusion

The Design of 14 bit pipeline ADC has been carried out in TSMC 018µm technology. The design is implemented in LT SPICE SWICHER CAD –III Schematic Editor and the results are verified with LT spice and simulation viewed in LT SPICE. The key Design module is summarized now. 3- TIQ Comparator is worn in single stage of ADC. An Analog multiplexer is used as DAC. An OPAMP has been used in analog adder. A unity gain Inverting amplifier is Designed using an OPAMP for sample and hold circuit. An Analog adder is designed using OPAMP. Shift register has been designed using d flip-flop. The overall Design is tested with various input signals and the results are obtained satisfactory for the specification. Because of convergence problem occurring in the tool only 14 -bit design of ADC is carried out. The 14-bit pipeline ADC is working up to 1 Ghz input frequencies